Digital Audio Transport, Conversion, And Multichannel DSP

What You Will Be Able To Do

• Separate audio encoding, channel layout, transport, physical connection, control bus, and converter hardware.
• Identify whether a source is outputting stereo PCM, a downmix, or an encoded surround payload.
• Choose where S/PDIF reception, surround decoding, sample-rate conversion, and DSP processing occur.
• Calculate I2S and TDM clock requirements and map channel slots.
• Build a clock-domain plan for one or more ADAU1701 processors.
• Document latency, mute, lock, channel order, and analog output limits.

The Six Layers

Three Useful Architectures

source S/PDIF PCM
→ digital receiver
→ I2S stereo
→ ADAU1701
→ four DAC outputs

source S/PDIF bitstream
→ receiver / detector
→ surround decoder
→ 6-channel PCM
→ TDM or I2S lanes
→ DSPs / DACs

HDMI source
→ HDMI audio receiver
→ multiple I2S streams or TDM
→ DSP channel map
→ DACs / amplifiers

1Identify The Actual Source Output

Record the source device, application, content format, output connector, and selected output mode. A menu that says “5.1” does not prove that six decoded PCM channels leave the connector.

• PCM or stereo: commonly two decoded channels on S/PDIF.
• Bitstream or passthrough: may carry an encoded surround payload when every stage supports it.
• Auto: may negotiate, downmix, or change format between programs.

2Define The Receiver And Decoder

A digital-interface receiver recovers the S/PDIF data, channel status, and clocks. A stream detector distinguishes PCM from supported non-PCM formats. A compatible decoder converts the encoded surround program into separate PCM channels.

3Write The PCM Contract

For every interface, record:

• sample rate
• word length and slot width
• signed format and justification
• channel count and order
• data lanes or TDM slot assignment
• full-scale and mute behavior

4Choose The Clock Architecture

Identify who supplies MCLK, BCLK, and frame clock at every serial link. Use one controller per clock net. If the source and DSP use independent clock domains, choose a receiver PLL, buffer, or ASRC architecture and document its limits.

shared-clock path:
source clock controller → receiver / DSP / DAC targets

independent-clock path:
source clock → receiver → ASRC → local DSP clock → DAC

5Calculate The Serial Bus

BCLK = sample rate × slots per frame × bits per slot

At 48 kHz, stereo with 32-bit slots needs 3.072 MHz BCLK. TDM8 with 32-bit slots needs 12.288 MHz. Confirm the timing limit of every connected device before selecting rate and slots.

6Map The ADAU1701

The ADAU1701 has two onboard ADC channels, four onboard DAC channels, and a serial input/output system capable of I2S-compatible, justified, and TDM operation. SigmaStudio exposes the analog ADCs separately from the serial input channels.

For the enclosed Wondom two-input/four-output unit, the normal RCA connectors remain analog. The programming or ICP connection is a control path. Multichannel serial-audio expansion requires actual access to the serial data and clock pins or purpose-built interface hardware.

7Plan More Than Four Outputs

Four onboard DACs limit one ADAU1701 to four direct analog outputs. Additional channels can be created through:

• external multichannel DACs connected to serial outputs
• another DSP receiving TDM or I2S audio
• multiple processors with a shared clock and coordinated control
• analog cascading, with the added DAC-to-ADC conversion and latency clearly documented

Controlling multiple DSPs over I2C or SPI is separate from transporting audio between them. Both addressing and audio clocks must be designed.

8Choose The Rate And Processing Budget

Use the rate required by the source, converter bandwidth, processing, latency, and bus architecture. Higher rates increase serial bandwidth and usually reduce the instructions available per sample. On the ADAU1701, double- and quadruple-rate modes trade processing budget for the higher rate.

9Add SRC Only Where Needed

Use synchronous SRC for a known rate relationship or ASRC to join independent clock domains. Record passband, stop-band, word length, latency, lock, and mute behavior. Do not pass an encoded surround payload through a PCM SRC unless the hardware explicitly supports that payload path.

10Control Word Length

Track source bits, serial slots, DSP arithmetic, and output words separately. Use rounding, saturation, and dither intentionally when reducing precision. A 32-bit slot does not create 32 meaningful bits, and floating-point processing does not remove ADC, DAC, or analog limits.

11Build Mute And Lock Handling

1. mute physical outputs before clock or source changes
2. wait for receiver, decoder, SRC, and PLL lock
3. verify PCM versus non-PCM state
4. confirm channel map and low-level output
5. unmute through a controlled ramp
6. define behavior for unlock, reset, communication loss, and power cycling

12Measure Latency And Channel Identity

Total latency includes receiver, decoder, buffering, SRC, DSP blocks, FIR filters, converters, and amplifier or network stages. Measure the complete path and keep all channels in the intended timing relationship.

Use one-channel identification signals to verify left, right, center, LFE, surround-left, and surround-right assignments before applying crossovers or summing.

Architecture Decision Table

Troubleshooting Matrix

Continue

• Print the Digital Audio Signal Path worksheet
• S/PDIF And Multichannel Audio
• I2S And TDM
• Clocking And Jitter
• Signal Flow, Routing, Summing, And Dynamics