Digital Audio Clocking And Jitter
Canonical Definition
Digital-audio clocking establishes when samples and serial bits are launched, captured, processed, and converted. Jitter is short-term timing variation of a clock edge from its ideal position, while drift and frequency offset describe slower rate error. Their effect depends on where the clock is used, signal frequency and level, interface tolerance, PLL or ASRC behavior, buffering, and converter architecture.
Common Clocks
| Clock | Job | Typical relationship |
|---|---|---|
| Frame clock / LRCLK / word select | marks one audio sample frame | usually equals sample rate |
| BCLK / SCLK | clocks serial data bits and slots | sample rate × slots × bits per slot |
| MCLK | high-frequency device or converter reference | often 64, 128, 256, 384, or 512 × sample rate |
| Recovered clock | derived from an encoded transport such as S/PDIF | depends on receiver and PLL |
Clock-Domain Choices
- Shared clock: one controller supplies the timing used by all connected targets.
- PLL recovery: a receiver derives a local clock from an incoming transport.
- FIFO or buffer crossing: temporary storage absorbs short timing differences but not unlimited drift.
- ASRC: resamples data between independent clock domains.
Bit-Perfect Does Not Prove Clock Quality
A data check can confirm that sample values arrived correctly. It does not by itself describe the sampling clock used by the final DAC, the receiver PLL, the analog output stage, or timing modulation at a converter boundary. Conversely, a small measured clock variation is not automatically audible; the resulting error depends on the complete architecture and signal.
Failure Modes
- two devices drive the same clock line
- no device supplies a required clock
- wrong edge, polarity, or duty cycle
- BCLK beyond device timing limits
- independent domains drift until samples repeat or drop
- receiver unlock is not muted safely
- probe loading or poor digital wiring creates apparent clock faults
Verification
- Draw every clock source and destination.
- Record controller and target roles.
- Measure rate, duty cycle, polarity, stability, and lock.
- Test interruption and relock behavior at low level.
- Measure audio noise or distortion only with the clock path and signal fully documented.