I2S And TDM Serial Audio
Canonical Definition
I2S and TDM are synchronous serial interfaces used to move decoded digital-audio sample words between integrated circuits or closely coupled boards. The link is defined by serial data, bit clock, frame or word-select timing, slot or word format, channel mapping, logic levels, and clock-controller roles. I2C and SPI may configure devices but are not the same audio-sample bus.
Signals
| Signal | Job |
|---|---|
| SDATA | serialized sample words |
| BCLK / SCLK | bit or slot timing |
| LRCLK / WS / frame sync | sample-frame or channel-slot reference |
| MCLK | optional high-frequency device reference |
| I2C / SPI | register and parameter control, not ordinary audio transport |
I2S, Justified Formats, And TDM
- I2S: the most-significant audio bit normally begins one BCLK after the word-select transition.
- Left-justified: the most-significant bit aligns with the frame edge.
- Right-justified: the least-significant bit aligns to the end of the slot.
- TDM: several channel slots share one frame, often on one serial data line.
Devices must agree on slot count, slot width, word length, data edge, frame polarity, and channel order.
Bit-Clock Calculation
BCLK = sample rate × slots per frame × bits per slot| Format | At 48 kHz |
|---|---|
| stereo, 32-bit slots | 48,000 × 2 × 32 = 3.072 MHz |
| TDM8, 32-bit slots | 48,000 × 8 × 32 = 12.288 MHz |
Check the exact receiver timing limit before increasing slots or rate.
ADAU1701 Mapping
The ADAU1701 input cell exposes the two onboard ADC channels first, followed by up to eight serial-input channels. In TDM mode the eight slots can arrive through one serial data input; in non-TDM modes several stereo serial data pins may be used. The serial-port register settings, multifunction-pin assignment, clocks, wiring, and SigmaStudio channel map all have to match.
The enclosed Wondom unit’s external ICP connector is primarily a control/programming connection. Multichannel digital-audio expansion requires physical access to the relevant serial-audio and clock signals or a board designed to expose them.
Safe Bring-Up
- Confirm logic voltage and common ground.
- Assign one clock controller.
- Verify MCLK if required, then frame clock and BCLK.
- Send one low-level channel or slot.
- Confirm data edge, format, word length, and channel map.
- Keep analog outputs muted until silence and channel identity are proven.