Digital Audio Signal Path Worksheet

Use one sheet per architecture or source mode. Record the complete encoding, transport, clock, channel, DSP, converter, and analog path before connecting amplifiers.

1. Project And Goal

Date / project:

Operator:

Vehicle / bench setup:

Required channels:

Stereo / 5.1 / 7.1 / custom:

Maximum latency goal:

Architecture question this sheet must answer:

2. Source And Content

Source hardware:

Application / playback mode:

Content format:

Native channel layout:

Source output setting:

PCM / bitstream / auto / downmix:

Connector:

Transport:

Volume, normalisation, bass management, dynamic range, and other source processing:

3. Receiver, Detection, And Decode

Stage	Hardware / firmware	Input	Output	Lock / status / notes
Physical receiver
PCM / non-PCM detector
Surround decoder
Sample-rate converter

Detected payload:

Decoded channel order:

Downmix mode:

Bass management / LFE handling:

4. PCM Contract

Sample rate:

Nominal word length:

Serial slot width:

Signed format:

I2S / left / right justified / TDM:

Frame polarity / data edge:

Number of data lanes:

Channels per lane:

Channel order and slot map:

Silence / mute code verified:

Full-scale convention:

5. Clock Map

Clock	Frequency	Controller	Targets	Measured / lock notes
MCLK
BCLK
LRCLK / frame sync
Recovered S/PDIF / HDMI clock
Local DSP clock

BCLK calculation:

Independent clock domains:

PLL / FIFO / ASRC crossing:

Unlock and relock behavior:

6. DSP And Converter Map

Channel	Serial lane / slot	DSP input	Processing / output	DAC / physical output
Left
Right
Center
LFE
Surround left
Surround right
Additional
Additional

DSP model / revision:

Core sample-rate mode:

Instruction / MIPS use:

Control bus and address:

External DAC / codec:

Additional DSPs:

Shared reset, boot, preset, and mute sequencing:

7. Word-Length And SRC Record

Input word length:

DSP internal format:

Output word length:

Rounding / saturation:

Dither distribution / level:

Noise shaping:

SRC input / output rates:

SRC latency / lock:

8. Latency Budget

Stage	Latency	Method / notes
Receiver / decode
SRC / buffering
DSP blocks
FIR / convolution
DAC / amplifier / network
Total

9. Safe Bring-Up

☐ analog outputs and amplifiers muted
☐ logic voltage and ground reference verified
☐ one clock controller per net
☐ MCLK, BCLK, and frame clock measured
☐ PCM / non-PCM status verified
☐ silence and low-level data tested
☐ one channel at a time identified
☐ source changes and relock tested
☐ outputs ramped up only after channel map passed

10. Final Verification

Architecture that passed:

Measured channel and clock failures:

What remains provisional:

Next hardware or firmware action:

Companion lesson: Digital Audio Transport, Conversion, And Multichannel DSP.